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SOC and IP Design Engineer, Google Cloud

GoogleHaifa и ещё 2 городаВ офисеот 4 лет
SOCSystemVerilogFPGARTL DesignLow-Power DesignDigital LogicLogic SynthesisIP Design

Описание

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services and Google Cloud.

Responsibilities

  • Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.)
  • Perform Register-Transfer Level (RTL) coding (coding and debug in Verilog, SystemVerilog), function/performance simulation debug, and Lint/CDC/FV/UPF checks
  • Participate in synthesis, timing/power closure activities
  • Participate in test plan and coverage analysis of the block and SoC-level verification
  • Communicate and work with multi-disciplined and multi-site teams

Requirements

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
  • 4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog
  • Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques
  • Experience with design sign-off and quality tools (e.g., Lint, CDC, etc.)
  • Experience with SoC or IP architecture

Nice to have

  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture
  • Knowledge of high-performance and low-power design techniques, assertion-based formal verification, Field-programmable Gate Array (FPGA) and emulation platforms, and SoC architecture
  • Knowledge in one of the following areas such as Double Data Rate (DDR)/Low Power Double Data Rate (LPDDR), High-bandwidth memory (HBM)
  • Excellent problem-solving and debugging skills

We offer

  • In most instances, this position requires in-person interviews as part of the hiring process