Senior Technical Program Manager, Chip DevOps and Methodology

Описание

As a Technical Program Manager for Chip DevOps, you will orchestrate the delivery of the foundational engineering environment and drive the execution of a unified silicon design methodology across our engineering organization. You will own the lifecycle of programs that scale our Electronic Design Automation (EDA) toolchains, optimize massive cloud compute grids, and establish standardized, automated workflows. This is a highly cross-functional role requiring a unique blend of modern cloud infrastructure expertise, semiconductor workflow awareness, and agile program management. You will partner closely with Design, Verification, CAD, and Infrastructure teams to eliminate fragmented workflows, implement standardized methodologies, and ensure a seamless, high-performance environment to build next-generation chips.

Responsibilities

• Manage programs the definition, standardization, and company-wide adoption of a unified design and verification methodology. Drive alignment on consistent coding standards, automated checks, Process Design Kits (PDK) management, and IP reuse protocols.
• Define, manage, and deliver complex infrastructure and CAD roadmaps, ensuring projects are completed on time, within budget, and with minimal disruption to design timelines.
• Manage programs the deployment, licensing, and scaling of EDA tools (e.g., Synopsys, Cadence, Siemens) across hybrid or fully cloud-based environments, ensuring tool flows strictly adhere to the unified methodology.
• Lead initiatives to optimize compute infrastructure (e.g., high-performance computing clusters, storage, and cloud instances) to manage massive simulation, synthesis, and physical design workloads.
• Drive the strategy and implementation of automated workflows, continuous integration, and continuous verification (CI/CD) pipelines.

Requirements

• Bachelor's degree in Engineering, Computer Science, or equivalent practical experience.
• 8 years of experience as a technical program manager or engineering lead.
• Experience in supporting unified design/verification methodologies (e.g., standardized UVM frameworks, unified linting/CDC rules, automated regression tracking) or experience with software engineering lifecycle management or Site Reliability Engineering (SRE) principles.
• Experience with the front-to-back silicon design lifecycle (e.g., RTL design, verification, synthesis, STA, place and route, tape-out) or experience in building automation, CI/CD pipelines, and Infrastructure as Code (IaC) environments for engineering workflows.

Nice to have

• Experience with cloud platforms optimized for High-Performance Computing (HPC), grid computing (e.g., LSF, Slurm), and massive storage architectures.
• Experience managing infrastructure and centralized configuration profiles for EDA tool suites.
• Experience managing complex vendor relationships (EDA vendors, cloud providers) and forecasting infrastructure compute budgets.
• Familiarity with modern infrastructure-as-code (IaC) and automation tools (e.g., Terraform, Ansible, Jenkins, Gitlab CI) adapted for hardware workflows.
• Proficiency in managing infrastructure and CAD roadmaps using Agile, Scrum, or Kanban frameworks tailored for hardware timelines.
• Exceptional ability to translate complex technical infrastructure and methodology needs into clear business/program outcomes for executives and vice versa.

We offer

• Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders; deep expertise in domain.
• Google is an equal opportunity and affirmative action employer.
• English proficiency is a requirement for all roles unless stated otherwise in the job posting.
• Google does not accept agency resumes.