Senior Silicon DFT Lead
GoogleTel Aviv и ещё 2 городаот 8 лет
HardwareASICDFTSiliconJTAGATPGMBIST
Описание
As the Design for Test (DFT) Engineer Lead, you will play a crucial role in DFT Architecture and DFT design, and support devices to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality throughout the project life-cycle, and providing sign-off DFT to tapeout.
Responsibilities
- Lead and execute DFT activities in the design, implementation, and verification solutions for Application-Specific Integrated Circuits (ASIC).
- Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
- Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
- Manage a DFT team planning, deliverables, and provide technical mentoring and guidance.
- Lead DFT execution of a silicon project, planning, execution, tracking, quality, and signoff.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
- 8 years of experience in Design For Test from DFT architecture to post silicon production support.
- 4 years of experience with people management.
- Experience with DFT design and verification for multiple projects, DFT specification, definition, architecture, and insertion.
- Experience with DFT techniques and common industry tools, DFT and Physical Design flows, and DFT verification flow.
- Experience in leading DFT activities throughout the whole ASIC development flow.
Nice to have
- Master's degree in Electrical Engineering or a related field.
- Experience in post-silicon Debug, test or product engineering.
- Experience in Joint Test Action Group (JTAG) and Internal JTAG (iJTAG) protocols and architectures.
- Experience in SoC cycles, silicon bring-up, and silicon debug activities.
- Knowledge of fault modeling techniques.
We offer
- Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc.