FE integration & STA IP Lead- Advanced Technologies Group

Описание

At Apple, we relentlessly strive to create products that enrich people’s lives. This role is for an IP timing Engineer who will empower us to produce fully functional first silicon IP designs. Your responsibilities will encompass all phases of pre-silicon development, from defining the constraints to achieving high-quality tape-out.

Responsibilities

• Own the entire IP-level netlist generation and timing convergence journey from synthesis to sign-off
• Drive synthesis, UPF power intent, scan insertion, and external IP integration
• Architect timing constraints for both standard and complex custom designs that ensure sign-off quality from day one
• Partner closely with RTL designers to deeply understand design intent and clock architecture
• Collaborate with CAD teams to shape and optimize cutting-edge flows
• Team with Physical Design engineers to achieve flawless timing sign-off
• Bring fresh perspectives to timing analysis methodologies
• Proactively identify and resolve timing challenges to eliminate pessimism and accelerate convergence

Requirements

• Bsc/Msc in Electrical Engineering
• 5+ years of experience in the field
• At least 2+ years of experience in writing ASIC timing constraints and achieving timing closure
• Expertise in STA tools (Primetime) and flow generation
• Knowledge of the ASIC design timing closure flow and methodology
• Understanding of timing corners/modes
• Familiarity with process variations and signal integrity-related issues
• Hands-on experience in generating and managing timing/SDC constraints
• Proficient in scripting languages (Tcl and Perl)
• Knowledge of synthesis, DFT, and backend-related methodologies and tools
• Strong communication skills are required, as you will interact with various groups

We offer

• Apple believes accessibility is a fundamental human right, reflected in culture, benefits, and digital tools
• Help build a career where you feel like you belong by welcoming as many perspectives as possible