Senior Hardware Technical Lead, Interconnect Systems

Описание

NVIDIA’s Interconnect Product Hardware Engineering team designs advanced test solutions for high-speed electro-optical devices powering next-generation AI data centers. This role involves owning end-to-end technical program execution of complex Co-Packaged Optics (CPO) and Silicon Photonics (SiPho) interconnect hardware, from concept through mass production. It is a senior individual contributor role with a strong leadership dimension.

Responsibilities

• Drive the full program lifecycle of advanced CPO and interconnect test solutions — from requirements through architecture, design, bring-up, characterization, qualification, and release to HVM — while continuously evaluating new technologies and methodologies.
• Act as the technical focal point across parallel workstreams including Board Design, Silicon Photonics, Opto-Mechanics, Thermal, FW/SW, DFT, Process Engineering, Manufacturing, and Quality — building integration plans and communicating status, priorities, risks, and dependencies to leadership.
• Mentor engineers, conduct design reviews, and deliver constructive feedback to elevate team capabilities and foster a culture of engineering excellence; influence, lead, and align multi-site, multi-disciplinary teams toward common goals.
• Consolidate requirements from internal stakeholders (Systems Engineering, Software, Marketing, Architecture, Production) into a comprehensive plan of record; coordinate resource allocation and team assignments in partnership with engineering management.
• Define and execute the validation and coverage strategy from die to system level — develop characterization plans, test methodologies, automation frameworks, and data analysis pipelines to validate product performance across environmental conditions (temperature, voltage, process corners).
• Perform hands-on electrical and optical debug, failure analysis, and failure segmentation using advanced lab equipment (oscilloscopes, spectrum analyzers, OPMs, BER testers, source meters); drive root-cause analysis of complex issues spanning electrical, optical, mechanical, thermal, and firmware domains.
• Develop scripting and automation solutions (Python) for test automation, data collection, hardware control (I2C, SPI), and production process optimization; own electrical specifications, peripheral equipment selection, and DFM/DFT guidelines.
• Partner with manufacturing and production engineering teams to build robust test solutions for mass production, improve yield and test coverage, and lead innovations that reduce test time and cost.

Requirements

• B.Sc. or M.Sc. in Electrical Engineering, Electro-Optics, Applied Physics, or a related field (or equivalent experience)
• 12+ years in hardware system engineering, characterization, and/or product engineering for electro-optical or high-speed communication products
• 5+ years serving as a technical lead across multi-disciplinary projects end-to-end
• Demonstrated success in technical program management — guiding complex hardware programs from concept through mass production
• Deep hands-on background in hardware design, lab bring-up, characterization, debug, and electrical specification review
• Proficiency in Python scripting, data analysis (JMP or equivalent), test automation, and hardware control interfaces (I2C, SPI, JTAG)
• Strong communication and interpersonal skills — able to influence and align senior stakeholders and global teams
• Self-driven ownership mindset; an end-to-end problem solver who thrives in a fast-paced, multi-project environment

Nice to have

• Hands-on experience with Co-Packaged Optics system integration and production
• Background in silicon photonics device characterization (lasers, modulators, detectors, waveguides)
• Familiarity with opto-mechanical design, DFM/DFT/DOE techniques, and qualification test processes
• Track record in cross-functional management — mentoring, team building, and performance management
• Collaboration with overseas manufacturing and mass-production partners (OSAT, JDM/ODM)