Chip Design Engineer

Описание

Annapurna Labs, as part of Amazon, is looking for a System Hardware Engineer to be part of defining, shaping and integrating solutions for the next generation of cloud platforms.

Responsibilities

• Define and provide feedback to design of Graviton servers and server components
• Work with design partners and manufacturer sites to enable the manufacturing of the Graviton based servers
• Review, identify and qualify second source electrical components to enable continuity of supply
• Continuously assess process capabilities and innovate to simplify processes, reduce cost, and shorten cycle time of Graviton server development and manufacturing
• Collaborates with cross functional team members to gain knowledge and improve product design, processes, and quality
• Work with upstream vendors and downstream customers to optimize the entire value stream and put together joint processes that will lead better cost and cycle time
• Willingness to travel 3–4 times per year (approximately 1 week per trip) to design partner and manufacturing sites

Requirements

• B.Sc. in Electrical Engineering (or equivalent)
• 6+ years of experience leading hardware products from design through mass production — including component selection, schematic/layout review, thermal/mechanical design, hardware-software interfaces, and production test development
• 6+ years of hands-on experience in high-speed board design and signal integrity, with practical lab work on interfaces such as DDR4/5, PCIe Gen4/5/6, 100/400GbE
• Demonstrated ability to conduct hardware bring-up, debug, and failure analysis in a lab environment — both on-site and at external design partner sites

Nice to have

• Experience with CPU and peripherals architecture and design, particularly for multi-socket or accelerator-attached (GPU/AI) server platforms
• Familiarity with PCIe Gen6, CXL, or high-speed SerDes interfaces and emerging interconnect standards for AI/ML workloads
• Ability to analyze signal integrity / power integrity simulation results (e.g., from Ansys HFSS, Keysight ADS/PathWave, Cadence Sigrity) and recommend design tuning actions — such as stackup adjustments, termination strategies, decoupling optimization, and trace routing improvements
• Practical experience with high-speed lab equipment (oscilloscopes, TDR, VNA, BER testers)
• Experience with sustaining engineering and production support — root cause analysis, ECO management, yield improvement, and vendor/CM collaboration
• Working knowledge of scripting and automation (Bash, Python) for lab data analysis, test automation, or design flow scripting — including familiarity with AI-assisted automation tools for engineering workflows
• Exposure to networking, storage, or Linux-based server environments
• Technical leadership skills — ability to drive cross-functional execution across layout, SI/PI, firmware, and manufacturing teams in a matrix organization, including collaborative design work with ODMs and external design partners — managing technical alignment, design reviews, and milestone tracking across organizational boundaries