Senior Chip Design Engineer, Graviton
AmazonHaifa и ещё 1 городот 5 лет
SOCSystemVerilogMicro-architectureChip DesignPCIeRTL DesignDDRAXIIP IntegrationSilicon Bring-upTape-out
Описание
Annapurna Labs is seeking a Senior Chip Design Engineer to join the Graviton product line team, developing leading-edge products on state-of-the-art process technologies for AWS, the world's largest cloud provider.
Responsibilities
- Act as the technical lead for a major SoC domain across its full lifecycle, from feature definition through tape-out and silicon bring-up
- Work with Product Definition and Architecture to turn product requirements into feature specifications for your domain
- Lead micro-architecture definition and own power, performance and area trade-offs, working with Physical Design and Software
- Drive RTL design in Verilog/SystemVerilog and lead design reviews for the domain
- Define and execute IP integration strategies
- Set verification priorities with the Verification and Emulation teams, and lead system-level and post-silicon debug for your domain
- Carry design learnings into the next Graviton generations, and improve design methodology and flows
- Mentor and technically guide engineers working in your domain, raising the technical bar of the team
Requirements
- 5+ years of experience in Chip Design
- Track record of owning a design domain from specification through tape-out
- Proficient in Verilog/SystemVerilog
- B.Sc. degree in Computer Engineering/Computer Science/Electrical Engineering
- Strong technical communication and mentoring capabilities
- Ability to lead technical work across teams and influence design decisions
Nice to have
- M.Sc. in a technical-related field
- Experience across multiple tape-outs, including post-silicon bring-up and debug
- Experience defining architecture and micro-architecture for complex SoC features
- Experience with IP integration and full chip development
- Protocols: PCIe, DDR, AXI, CHI, Ethernet
- Hands-on design experience with hardware support for virtualization and IO virtualization (e.g., hypervisors, Arm virtualization extensions, two-stage address translation, IOMMU/SMMU)