Wireless SoC Design Verification Engineer

Описание

As a Wireless Design Verification Engineer, you will be part of a team that is responsible for pre-silicon RTL verification of communication subsystems, SoC sub-systems and chip-level functionality. The activity may focus on block level, sub-system level or chip level, including end-to-end simulations of the entire data/control path. You will interact with DV methodologists, designers and communication systems engineers to develop reusable testbench and verification environment deploying the latest methodology with metric driven verification.

Responsibilities

• Own critical block and sub-system verification of wireless SoC projects
• Architect and develop testbenches and environments, by using state-of-the-art verification methodologies
• Define verification plan, create, simulate and debug test scenarios
• Drive regression and coverage analysis to ensure high quality DV
• Collaborate with design and systems engineering teams to review requirements, specifications and architecture, extract features and define DV attribute

Requirements

• BSc or MSC in Electrical Engineering or Computer Engineering
• 5+ years of verification experience
• Solid verification skills in problem solving, constrained random testing, and debugging
• Advanced knowledge of SystemVerilog and DV methodologies
• Self-motivated and dedicated with proven creative thinking capabilities
• Ability to handle multiple tasks and prioritise work to meet deadlines

Nice to have

• Experience with MAC or PHY Verification - a plus

We offer

• At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.