Graduate Digital Design Engineer

Описание

Responsibilities

• Write and debug RTL (Verilog/SystemVerilog) for blocks within 5G baseband DSP cores and hardware accelerators, under the guidance of senior engineers.
• Translate block-level specifications into clean, well-documented, synthesizable designs.
• Run lint, synthesis and timing analysis on your blocks, and help resolve the issues they raise.
• Support verification engineers in bringing up testbenches, debugging failures and reaching coverage goals.
• Take part in design reviews and learn to weigh power, performance and area (PPA) trade-offs.
• Work with algorithm, verification and backend teams to understand how your blocks fit into the full modem.

Requirements

• B.Sc. in Electrical or Computer Engineering (recent graduates)
• An experience in digital or VLSI design from student projects or internships.
• Solid grasp of digital design fundamentals: logic design, FSMs, pipelining, clocking and timing
• Basic familiarity with simulation and EDA tools (Synopsys, Cadence, Siemens EDA/Mentor or similar)
• Eagerness to learn, good problem-solving skills and clear communication in English

Nice to have

• Hands-on RTL design in Verilog or SystemVerilog, from academic or industry projects
• M.Sc. in Electrical Engineering
• Coursework or projects in signal processing or digital communication systems
• Scripting skills (Python, Tcl or Perl) for design automation