Junior SI/PI and Packaging Engineer

Описание

The SIP (Signal-Integrity & Packaging) team is part of Annapurna Labs' Chip development team, dealing with the external electrical interfaces of the device from Signal/Power-integrity and electrical usage perspectives. The team works closely with the BackEnd team to integrate interfaces to the Die, designs the BGA's substrate package layout, performs Signal and power integrity simulations, and collaborates with the system team for optimal pin-out and PCB breakout schemes.

Responsibilities

• Work on advanced high-speed interfaces such as PCIe, DDR and Ethernet.
• End-to-end solution of high-speed interfaces; from floor-planning at the DIE level, through Package and PCB routing, addressing both robust SI/PI considerations as well as optimizing layout routing.
• Signal and power integrity modeling and simulation of high-speed interconnects using advanced SI/PI simulation tools.

Requirements

• BSc in Electrical Engineering or in related field.
• 1-3 years of experience in board design, or lab measurement of digital high-speed interfaces or layout or physical design.
• Familiarity with Signal and Power integrity simulation tools.

Nice to have

• Experience with high-speed digital interfaces such as DRAM/PCIe/SerDes.
• Previous experience with lab equipment (e.g oscilloscope, spectrum analyzer).
• Experience with simulation/extraction tools (e.g. HFSS, Sigrity, HSpice).

We offer

• Unique entry point into a diverse and multidisciplinary domain.