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CPU Verification Engineer

AppleIsraelот 5 лет
C++SOCVerificationSystemVerilogRTLScriptwritingCPUEmulationCache CoherenceMemory Subsystem

Описание

This role involves working with elite CPU and SOC teams at Apple to deliver groundbreaking products.

Responsibilities

  • Establish DV methodology
  • Develop test-plans
  • Develop verification environment including stimulus and checkers
  • Write tests
  • Debug issues
  • Manage coverage
  • Sign-off for RTL freeze and tape-out
  • Play a critical role in end-to-end verification of memory subsystem by developing an in-depth understanding of cache coherence protocols and functioning of various units in CPU/SOC relevant to memory subsystem verification
  • Develop verification environment for both simulation and emulation
  • Develop synthesizable transactors and test benches
  • Support verification hooks for verifying memory subsystem functionality and CPU/SOC features
  • Develop unit level stimulus as well as full chip assembly or C programs to verify memory subsystem functionality
  • Develop verification IPs for utilization by Apple teams worldwide
  • Work closely with CPU/SOC RTL teams across US and Israel to understand specifications for developing verification strategy
  • Develop coverage monitors and accomplish coverage goals for design closure
  • Develop abstract end-to-end checks to verify CPU-SOC memory subsystem interaction and coherence protocols

Requirements

  • 5+ years of processor verification experience
  • In-depth knowledge of digital logic design, CPU and SOC architecture/micro-architecture and memory subsystem
  • Strong programming (C/C++, Verilog, Scripting), software optimization, and performance improvement skills
  • Experience in unit and full chip level test benches
  • Experience in developing testplans, assertions, and developing stimulus
  • Team player with excellent communication skills
  • Ability to work independently on verification efforts for a block/area of the design

Nice to have

  • Experience with emulation and developing synthesizable transactors