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Design Verification Engineer - Camera

AppleIsraelот 2 лет
PythonC++SystemVerilogPerlUVMTCLHardware AccelerationSOC VerificationMedia IP

Описание

The Pixel DV group works on complex, large-scale media IPs, partnering with architecture and design teams to deliver high quality media IP and systems.

Responsibilities

  • Develop verification test plans, test benches, tools and infrastructure, protocol monitors and agents, and coverage driven stimulus
  • Apply advanced techniques to achieve verification with the highest quality, productivity, and time-to-market
  • Apply deep system level understanding to find system architecture bugs, verifying the DUT at multiple levels - from block level to the entire IP and subsystem, with additional emphasis on power (NLP) and performance
  • Work closely with the design and architecture teams from the early stages of feature definition, to ensure timely delivery of quality designs
  • Work with methods to accelerate verification time
  • Be involved with Post Silicon Validation and other verification teams

Requirements

  • +2 years experience in SoC Verification, media IP verification experience is a plus
  • Advanced knowledge of SoC/Media IP architecture/design & in-depth knowledge of verification flow
  • Deep understanding and shown experience in advanced verification process, including dynamic and coverage based
  • Scripting and programming experience using several of the following: Python, Perl, e, SystemVerilog, C++, and TCL
  • Good interpersonal and collaboration skills, to work with partner Design and Architecture teams

Nice to have

  • Familiarity with verification environments, UVM, SysteMVerilog
  • Knowledge of hardware acceleration

We offer

  • Accessibility is reflected in the culture, benefits and digital tools