IP Pixel RTL Design Engineer

Описание

The HDC pixel group is working on Apple ISP (Image Signal Processing) IP development. The group implements highly complex cutting-edge image processing technologies, putting emphasis on quality and security, while meeting aggressive area and power constraints.

Responsibilities

• Participate in the architecture of next generations of Apple ISP
• Handle RTL implementation of the micro-architecture
• Participate in clearly defining specification, testing and verification of the designs
• Work in collaboration with CAD & PD teams to implement RTL design into GDS
• Run various flows and provide guidelines to other designers
• Participate in establishing CAD and design methodologies for correct by construction designs
• Handle micro architecture & RTL implementation as well as front-end work and top-level aspects of the design, such as performance and more
• Work closely with DV teams to verify blocks and SoCs and with PD for design implementation

Requirements

• 6+ years of Logic Design experience
• Advanced knowledge of ASIC RTL design methodologies
• Advanced knowledge of standard ASIC verification flows including simulation and testbench development
• Working knowledge of frontend tools (Synthesis, STA, etc
• Excellent knowledge of System Verilog, Verilog
• Good knowledge of C / C++
• Experience with either Python/Perl/Tcl scripts
• Knowledge of industry standard interfaces and experience with multiple frontend simulators/debuggers
• A teammate with excellent interpersonal skills and the desire to pursue diverse challenges
• BS.c / MS.c EE or BS.c / MS.c CE

Nice to have

• Hands-on experience with signal processing design
• Knowledge of formal verification & methodologies