IP Design Verification Engineer

Описание

This role is for a Design Verification Engineer who will enable us to produce fully functional first silicon IP designs.

Responsibilities

• Ensure bug-free first silicon for part of the IP
• Develop detailed test and coverage plans based on the micro-architecture
• Develop verification methodology suitable for the IP, ensuring a scalable and portable environment
• Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage and more

Requirements

• 7+ years’ experience in digital logic design verification
• Basic knowledge of SystemVerilog and UVM
• Experience developing UVM based IP test-benches
• Experience with complex designs and advanced debug skills ability
• Experience with verification tools such as simulators, waveform viewers, build/run automation, coverage collection and analysis, gate level simulations
• Strong communication skills
• Ability to work well in a team and be productive under tight schedules
• BS.c or MS.c in Electrical Engineering

Nice to have

• Excellent knowledge of one of the scripting languages: Python, Perl, TCL
• Experience with serial/parallel protocols such as PCIe or DRAM
• Proven knowledge of formal verification methodology
• C/C++ experienced level knowledge in lieu of UVM knowledge
• Experience with Lab hands-on debug

We offer

• Opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers